Effective Compiler Generation by Architecture Description

Stefan Farfeleder and Andreas Krall and Edwin Steiner and Florian Brandner

Institut für Computersprachen
Technische Universität Wien
Argentinierstraße 8
A-1040 Wien, Austria



Embedded systems have an extremely short time to market and therefore require easily retargetable compilers. Architecture description languages (ADLs) provide a single concise architecture specification for the generation of hardware, instruction set simulators ands compilers. In this article, we present an ADL for compiler generation. From a specification, we can derive an optimized tree pattern matching instruction selector, a register allocator and an instruction scheduler. Compared to a hand-crafted back end, the generated compiler produces smaller and faster code.

The ADL is rich enough that other tools, such as assemblers, linkers, simulators and documentation, can all be obtained from a single specification.