Using 16KB D-cache on the 21064a under Linux

The 21064a (aka EV45) comes with 16KB of L1 D-cache. The processor can use that cache in two modes: as 8KB direct-mapped cache or as 16KB virtually-indexed direct-mapped cache. The MILO and Linux kernel that we used ran the processor in 8K mode (I have a report of getting 16K by booting via SRM, probably without MILO). Here you find a kernel module that allows you to toggle between these modes; you find a description of how to compile and run it and warnings about using it in the source code.

The speedup we saw for our LaTeX benchmark was 5%; and the difference is also visible in the lmbench results.

I was worried about cache consistency issues arising with the virtually indexed cache. Therefore I have written a test program for checking this. The result is that the test went well even with 16K D-cache. My guess is that the hardware invalidates the other cached instance of the same physical memory location automatically with bus snooping logic or somesuch.

This module has been tested successfully on a Cabriolet booted with ARC and MILO. The latest version of this module reportedly fixes the problems that have been reported for the Avanti. It probably won't work if you boot with SRM without MILO (but it's probably not necessary then). Please report any positive and negative experiences to

Related stuff:

Anton Ertl
[ICO]NameLast modifiedSizeDescription

[DIR]Parent Directory  -  
[   ] 13:48 23K 
[TXT]mapcheck.c13-Mar-1999 18:22 1.5K 
[   ]milo-2.0.35-c5.5.tar.gz24-Mar-1999 16:00 1.4M 
[TXT]toggle_dc_16k.c26-Mar-1999 17:10 3.2K 

Apache/2.2.22 (Debian) DAV/2 mod_fcgid/2.3.6 PHP/5.4.36-0+deb7u3 mod_python/3.3.1 Python/2.7.3 mod_ssl/2.2.22 OpenSSL/1.0.1e mod_perl/2.0.7 Perl/v5.14.2 Server at Port 80