An Open Notation for Memory Tests

Ad J. van de Goor, Aad Offerman, and Ivo Schanstra: Towards a Uniform Notation for Memory Tests (presented at the European Design & Test Conference and Exhibition 96)

Aad Offerman and Ad J. van de Goor: An Open Notation for Memory Tests (presented at the IEEE International Workshop on Memory Technology, Design and Testing, 1997)

There is a font issue here. I have emailed Adrian Offerman to find out if he knows of a font that contains the symbols used here. He sent me his xbm bitmaps, but they are in the Symbol and Wingdings fonts in Word. The only remaining issue is how to make them display in HyperTerminal.

Memory Test Verification and Generation

A. Offerman, Automatic Verification and Generation of Memory Tests (Masters thesis, August 1995)

While it is certainly possible to program this piece, it would not be appropriate to put this into an embedded environment. At best, this would be an off-line activity.

Simplified notation for terminals

Terminal font has single arrows

2 up/down = 0x12 = ^R

$ down = 0x19 = ^Y

# up = 0x18 = ^X

Standard test algorithms

S. Hamdioui, R. Wadsworth, J.D. Reyes, and A.J. van de Goor, Memory Fault Modeling Trends: A Case of Study (Journal of Elecronic Testing, Thoery and Application JETTA, Vol. 20, pp. 245-255, 2004)

Alexander Paalvast, Testing Single Inline Memory Modules (SIMMs) Theory and practice (Masters thesis, December 1999)

Trade off complexity with fault detection. On-going maintenance of test notation parser determines what is possible.

Table 1. Examples of base tests (BTs).

No. BT name Test length Description

1 SCAN [1] 4n {⇑ (w0);⇑ (r 0);⇑ (w1);⇑ (r1)}

2 MATS+ [16] 5n {ô(w0);⇑ (r0,w1);⇓ (r1,w0)}

3 MATS++ [6] 6n {ô (w0);⇑ (r0,w1);⇓ (r1,w0, r0)}

4 March C− [14, 18] 10n {ô (w0);⇑ (r0,w1);⇑ (r1,w0);⇓ (r0,w1);⇓ (r1,w0); ô (r0)}

5 PMOVI [8] 13n {⇓ (w0);⇑ (r0,w1, r 1);⇑ (r1,w0, r 0);

⇓ (r0,w1, r 1);⇓ (r1,w0, r0)}

6 March SR [9] 14n {⇓ (w0);⇑ (r0,w1, r1,w0);⇑ (r0, r 0);

⇑ (w1);⇓ (r1,w0, r0,w1);⇓ (r1, r1)}

7 March SS [11] 22n {ô (w0);⇑ (r0, r0,w0, r0,w1);⇑ (r1, r1,w1, r1,w0);

⇓ (r0, r0,w0, r0,w1);⇓ (r1, r1,w1, r1,w0); ô (r0)}

8 March G [17] 23n {ô (w0);⇑ (r0,w1, r1,w0, r0,w1);⇑ (r1,w0,w1);

⇓ (r1,w0,w1,w0);⇓ (r0,w1,w0);⇑ (r0,w1, r 1);⇑ (r1,w0, r0)}

9 March RAW [10] 26n {ô (w0);⇑ (r0,w0, r0, r0,w1, r 1);⇑ (r1,w1, r1, r1,w0, r 0);

⇓ (r0,w0, r0, r0,w1, r 1);⇓ (r1,w1, r1, r1,w0, r 0); ô (r0)}

10 Hammer [19] 49n {⇑ (w0);⇑ (r0, 10 ∗ w1, r 1);⇑ (r1, 10 ∗ w0, r 0);

⇓ (r0, 10 ∗ w1, r 1);⇓ (r1, 10 ∗ w0, r0)}

11 GalColumn 6n+4nR {⇑ (w0);⇑b (w1b, col(r0, r1b),w0b);

⇑ (w1);⇑b (w0b, col(r1, r0b),w1b)}

12 GalRow 6n+4nC {⇑ (w0);⇑b (w1b, row(r0, r1b),w0b);

⇑ (w1);⇑b (w0b, row(r1, r0b),w1b)}

13 WalkColumn 8n+2nR {⇑ (w0);⇑b (w1b, col(r0), r1b,w0b);

⇑ (w1);⇑b (w0b, col(r1), r1b,w0b)}

14 WalkRow 8n+2nC {⇑ (w0);⇑b (w1b, row(r0), r1b,w0b);

⇑ (w1);⇑b (w0b, row(r1), r1b,w0b)}

[1] M.S. Abadir and J.K. Reghbati, “Functional Testing of Semiconductor Random Access Memories,” ACM Computer Surveys, vol. 15, no. 3, pp. 175–198, 1983.

[6] M.A. Breuer and A.D. Friedman, Diagnosis and Reliable Design of Digital Systems, Woodland Hills, CA, USA: Computer Science Press, 1976.

[8] J.H. De Jonge and A.J. Smeulders, “Moving Inversions Test Pattern is Thorough,Yet Speedy,” Comp. Design, 1976, pp. 169–173.

[9] S. Hamdioui and A.J. van de Goor, “Experimental Analysis of Spot Defects in SRAMs: Realistic Fault Models and Tests,” Proc. of Ninth Asian Test Symposium, 2000, pp. 131–138.

[10] S. Hamdioui, Z. Al-Ars, and A.J. van de Goor, “Testing Static and Dynamic Faults in Random Access Memories,” Proc. of IEEE VLSI Test Symposium, 2002, pp. 395–400.

[11] S. Hamdioui, A.J. van de Goor, and M. Rodgers, “ March SS: A Test for All Static Simple RAM Faults,” Proc. IEEE InternationalWorkshopon Memory Technology, Design, and Testing, 2002, pp. 95–100.

[14] M. Marinescu, “Simple and Efficient Algorithms for Functional RAM Testing,” in Proc. of International Test Conference, 1982, pp. 236–239.

[16] R. Nair, “An Optimal Algorithm for Testing Stuck-at Faults Random Access Memories,” IEEE Trans. on Comp., vol. C-28, no. 3, pp. 258–261, 1979.

[17] D.S. Suk and S.M. Reddy, “A March Test for Functional Faults in Semiconductors Random-Access Memories,” IEEE Trans. on Comp., vol. C-30, no. 12, pp. 982–985, 1981.

[18] A.J. van de Goor, Testing Semiconductor Memories, Theory and Practice, ComTex Publishing, Gouda, The Netherlands, 1998.

[19] A.J. van de Goor and J. de Neef, “Industrial Evaluation of DRAMs Tests,” Proc. of Design Automation and Test in Europe, 1999, pp. 623–630.