Institute of Computer Languages
Compilers and Languages Group
über
| Datum: | Freitag, den 4. Oktober 2013 |
|---|---|
| Zeit: | 10:00 Uhr s.t. *) |
| Ort: | TU Wien, Bibliothek E185.1, Argentinierstraße 8, 4. Stock (Mitte) |
| *) Tee: | 9:30 Uhr in der Bibliothek E185.1, Argentinierstraße 8, 4. Stock (Mitte) |
In the next years, real-time embedded systems will be built on multicore platforms which provide better energy efficiency than current single-core architectures. Such multicore platforms challenge timing analysis techniques: sharing hardware resources among cores generates conflicts that impair the timing predictability. This observation has inspired several FP7 European projects that have designed or are still designing time-predictable multicore architectures. In this talk, we assume that such platforms are available and we look forward to the next step which will be the parallelisation of critical applications. This will be needed to achieve the high performance requirements that are foreseen to get support for even more functionalities like better safety, lower emissions and improved comfort for passengers in aircrafts or cars.
How real-time applications can be efficiently parallelised to make their timing analysis feasible is a question at the heart of the parMERASA project which gathers academic and industrial partners from the avionics, automotive and construction machinery domains. Within this scope, a pattern-supported approach to parallelisation is being designed and time-predictable operating systems services are investigated. Besides, new techniques for the timing analysis of parallel applications must be designed to take interactions among threads (e.g. delays due to synchronisations) into account. We will present our approach to account for these interactions when estimating the worst-case execution time (WCET) of a parallel program. This approach has been successfully implemented in OTAWA, a toolset dedicated to WCET analysis, and experimented on benchmarks and applications from the industry.
Christine Rochange is a full professor in Computer Science at the University of Toulouse. She is a member of the IRIT research lab. Her research interests include the analysis of worst-case execution times (WCET). Her contributions concern the modelling of hardware platforms, the design of time-predictable architecture and the timing analysis of parallel real-time applications. She participates in the parMERASA European project that investigates multicore architectures, system-software, parallelisation approaches and verification tools for hard real-time systems.( http://www.irit.fr/~Christine.Rochange/)
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