One distinctive feature of VADL lies in its separation of the instruction set architecture (ISA) specification and the microarchitecture (MiA) specification. This segregation allows users the flexibility to combine various ISAs with different MiAs, providing a versatile approach to processor design. In contrast to existing PDLs, VADL's MiA specification operates at a higher level of abstraction, enhancing the clarity and simplicity of the design process. Notably, with a single ISA specification, VADL streamlines compiler generation and maintenance by eliminating the need for intricate compiler-specific knowledge.
A detailed description of VADL can be found on arXiv
We plan to release VADL as open source. As main parts are proprietary software a rewrite of the complete system is necessary. The implementation language of VADL is JAVA 21 or higher. To improve the performance and functionality of the system it is additionally necessary to develop a new parser, optimize the instruction decoder, reimplement and improve the assembler and linker generator, add support for GCC, add support for superscaler micro architectures, add floating point support, add automatic test generation, add support for tensor instructions in the compiler, simulator and hardware generator and improve the documentation generation.
Bachelor projects must be doable in 250 to 300 hours. Therefore, only a small subset of the topics are available. Possible small topics are rewrite (parts of) the generic compiler infrastructure, develop an optimized decoder generator, specify new architectures in VADL, develop simple test generators, rewrite the assembler parser generator and enhance it to support an attribute grammar.